1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a device for testing such a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device suitable for a delay test using a scan path test circuit, and a device for testing such a semiconductor integrated circuit device.
2. Description of the Related Art
Semiconductor integrated circuit devices (hereinafter referred to as “LSI chips”), recently available in larger scale integration and higher densities, which are not designed for an easy testing configuration, cannot be tested and diagnosed for faults. One known approach for easy testing is a scan path process in which flip-flops in a semiconductor integrated circuit are connected into a chain pattern so as to operate as a shift register, and when the circuit is tested, the values of the flip-flops are controlled and observed from outside of the circuit based on the function as the shift register.
For testing an LSI chip according to the scan path process, the LSI chip incorporates a plurality of scan flip-flops which are flip-flops for use in normal operation and testing, and their input and output terminals for testing are connected in series, i.e., cascade, to connect the flip-flops as a shift register.
The scan flip-flops have a normal operating function to operate normally as ordinary flip-flops, and also have a scan function to operate as scan flip-flops with a scan clock SC as a testing clock while a scan-in signal SIN as a testing pattern signal is being supplied as a data input signal.
According to the scan path process, the scan-in signal SIN as a testing pattern signal is input to a scan path test circuit which is constructed of the cascaded scan flip-flops to set the scan flip-flops to desired values, and thereafter the scan flip-flops are operated normally and output values, i.e., scan-out signals SOUT, of the scan flip-flops which have been operated normally are observed to determine whether the logic operation of the LSI chip is normal or not.
LSI chips available in recent years are not only of larger-scale integration and higher-density designs, but also are operable at higher speeds. Therefore, they need to be checked not only for normal logic operation, but also for normal operation at a clock frequency prescribed according to product specifications.
According to a conventional LSI chip testing process, a delay test is conducted. As shown in FIG. 1A of the accompanying drawings, scan flip-flops (scan F/F) are connected into a chain-like pattern, and then, as shown in FIG. 1B of the accompanying drawings, two pulses spaced from each other by a pulse interval (“Spec” in FIG. 1B) corresponding to the period of a clock signal (having a frequency of 100 MHz or higher, for example) prescribed according to product specifications are input as clocks A, B in FIGS. 1A and 1B from a testing device to a given path (Path). Output values from desired two flip-flops are observed to determine whether the LSI chip malfunctions due to a delay caused by elements such as logic circuits or not.
In the conventional LSI chip testing process, the two in the delay test are generated by an LSI tester, and supplied directly to the scan path test circuit in the LSI chip.
The conventional LSI chip testing process is problematic in that since a frequency which can be used in the delay test depends on the performance of a driver circuit of the LSI tester for outputting the two pulses, LSI chips which operate at high speeds cannot be put to the delay test unless the LSI tester is expensive enough to output high-speed pulses. Specifically, recent LSI chips have internal clock frequencies up to several hundreds MHz, and very expensive LSI tester is needed to test such LSI chips.